系统时钟 | taohu的站

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时钟分类：

内核时钟（SYSCLKOUT）

外设时钟

低速时钟（LSPCLK）
高速时钟（HSPCLK）

⭐内核时钟 1️⃣原理框图 2️⃣寄存器 3️⃣频率计算 4️⃣PLL工作模式 5️⃣PLL配置流程 6️⃣范例程序 ⭐外设时钟

⭐内核时钟

1️⃣原理框图

2️⃣寄存器

PLLSTS

MCLKSTS(缺失时钟状态，0正常，1缺失)
MCLKOFF（缺失时钟检查关闭，1关闭）
PLLLOCKS（当PLLLOCKS=1，才可以改变DIVSEL）
PLLOFF（PLLOFF位置1可将PLL模块关闭）
DIVSEL（分频系数，0，1四分频；2，二分频；3，一分频）

PLLCR

DIV（乘法器系数，4bit，0-10）

3️⃣频率计算

4️⃣PLL工作模式

关闭	将PLLCR寄存器设为0x0000,PLLOFF位置1
旁路	上电复位或复位后，PLL进入该模式但PLL 模块却未关闭。
使能	向PLLCR寄存器中写入非零的数可使能PLL 模块

详细描述

5️⃣PLL配置流程

6️⃣范例程序

初始PLL代码


void InitPll(Uint16 val, Uint16 divsel)
{

   // Make sure the PLL is not running in limp mode
   if (SysCtrlRegs.PLLSTS.bit.MCLKSTS != 0)
   {
      // Missing external clock has been detected
      // Replace this line with a call to an appropriate
      // SystemShutdown(); function.
      asm("        ESTOP0");
   }

   // DIVSEL MUST be 0 before PLLCR can be changed from
   // 0x0000. It is set to 0 by an external reset XRSn
   // This puts us in 1/4
   if (SysCtrlRegs.PLLSTS.bit.DIVSEL != 0)
   {
       EALLOW;
       SysCtrlRegs.PLLSTS.bit.DIVSEL = 0;
       EDIS;
   }

   // Change the PLLCR
   if (SysCtrlRegs.PLLCR.bit. != val)
   {

      EALLOW;
      // Before setting PLLCR turn off missing clock detect logic
      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1;
      SysCtrlRegs.PLLCR.bit.DIV = val;
      EDIS;

      // Optional: Wait for PLL to lock.
      // During this time the CPU will switch to OSCCLK/2 until
      // the PLL is stable.  Once the PLL is stable the CPU will
      // switch to the new PLL value.
      //
      // This time-to-lock is monitored by a PLL lock counter.
      //
      // Code is not required to sit and wait for the PLL to lock.
      // However, if the code does anything that is timing critical,
      // and requires the correct clock be locked, then it is best to
      // wait until this switching has completed.

      // Wait for the PLL lock bit to be set.

      // The watchdog should be disabled before this loop, or fed within
      // the loop via ServiceDog().

	  // Uncomment to disable the watchdog
      DisableDog();

      while(SysCtrlRegs.PLLSTS.bit.PLLLOCKS != 1)
      {
	      // Uncomment to service the watchdog
          // ServiceDog();
      }

      EALLOW;
      SysCtrlRegs.PLLSTS.bit.MCLKOFF = 0;
      EDIS;
    }

    // If switching to 1/2
	if((divsel == 1)||(divsel == 2))
	{
		EALLOW;
	    SysCtrlRegs.PLLSTS.bit.DIVSEL = divsel;
	    EDIS;
	}

	// If switching to 1/1
	// * First go to 1/2 and let the power settle
	//   The time required will depend on the system, this is only an example
	// * Then switch to 1/1
	if(divsel == 3)
	{
		EALLOW;
	    SysCtrlRegs.PLLSTS.bit.DIVSEL = 2;
	    DELAY_US(50L);
	    SysCtrlRegs.PLLSTS.bit.DIVSEL = 3;
	    EDIS;
    }
}